Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64854 )
Change subject: soc/intel: Rename heci_init to cse_init ......................................................................
soc/intel: Rename heci_init to cse_init
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone).
BUG=none TEST=Able to build and boot google/taeko.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c 9 files changed, 15 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64854/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3f29fc3..48d9a6f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -133,7 +133,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* Initialize HECI interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) pre_mem_debug_init(); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 236a122..1ea91da 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -125,7 +125,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d284a9d..e01b1cf 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -85,11 +85,11 @@ }
/* - * Initialize the device with provided temporary BAR. If BAR is 0 use a + * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been * assigned yet and devices are not enabled. */ -void heci_init(uintptr_t tempbar) +void cse_init(uintptr_t tempbar) { pci_devfn_t dev = PCH_DEV_CSE;
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 8fd8ba0..28bc250 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -326,8 +326,12 @@ uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA]; } __packed;
-/* set up device for use in early boot enviroument with temp bar */ -void heci_init(uintptr_t bar); +/* + * Initialize the CSE device. + * + * Set up CSE device for use in early boot environment with temp bar. + */ +void cse_init(uintptr_t bar);
/* * Send message from BIOS_HOST_ADDR to cse_addr. diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index ecbdd97..39a5a332 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 1dc618c..8575a3f 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -114,7 +114,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index f7e6a91..3a2f8b4 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 7e891b1..30401fc 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -129,7 +129,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 872cca5..3c6e634 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake);