[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: add TCC activation functionality

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41855 )

Change subject: soc/intel/common: add TCC activation functionality
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Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41855/9/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cpu/cpulib.c:

https://review.coreboot.org/c/coreboot/+/41855/9/src/soc/intel/common/block/... 
PS9, Line 271: 	msr = rdmsr(MSR_TEMPERATURE_TARGET);
             : 	/* Time Window Tau Bits [6:0] */
             : 	msr.lo &= ~0x7f;
             : 	msr.lo |= 0xe6; /* setting 100ms thermal time window */
             : 	wrmsr(MSR_TEMPERATURE_TARGET, msr);
> I think it's a good idea to add us to the patches when making changes on APL specific code.

The issue here was not the FAN window but the fact that on Apollo Lake the Bits 0..7 in MSR 0x1A2 (MSR_TEMPERATURE_TARGET) are marked as reserved. They do exist on Tigerlake though.
So once a write access to this bits has happened, the CPU starts hanging...which is a valid behaviour when reserved bits are written.

@Sumeet: Yes, it would be nice if you can add us to the patches which are touching APL code.