[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add support to enable ISH FSP UPDs

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47104 )

Change subject: soc/intel/tigerlake: Add support to enable ISH FSP UPDs
......................................................................

soc/intel/tigerlake: Add support to enable ISH FSP UPDs

Add support to enable PchIshI2cEnable and PchIshGpEnable
fsp upds from devicetree.

BUG=none
TEST=Build mainboard using TGL.

Signed-off-by: Bora Guvendik 
Change-Id: I3ba05e9588ba2e75c9f49168568ff9850ab67abe
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
3 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47104/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 492d6fd4..f902449 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -109,6 +109,14 @@
    hex
    default 0x10000

+config MAX_ISH_GP_PINS
+	int
+	default 8
+
+config MAX_ISH_I2C_CONTROLLERS
+	int
+	default 3
+
 config MAX_ROOT_PORTS
    int
    default 12
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f752b5f..8462571 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -492,6 +492,10 @@
     *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
     */
    uint8_t PchPmPwrCycDur;
+
+	/* Ish related */
+	uint8_t PchIshGpEnable[CONFIG_MAX_ISH_GP_PINS];
+	uint8_t PchIshI2cEnable[CONFIG_MAX_ISH_I2C_CONTROLLERS];
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 887241b..c209230 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -188,6 +188,13 @@
    	params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
    }

+	/* Ish Configs */
+	for (i = 0; i < CONFIG_MAX_ISH_GP_PINS; i++)
+		params->PchIshGpEnable[i] = config->PchIshGpEnable[i];
+
+	for (i = 0; i < CONFIG_MAX_ISH_I2C_CONTROLLERS; i++)
+		params->PchIshI2cEnable[i] = config->PchIshI2cEnable[i];
+
    /* Enable ClkReqDetect for enabled port */
    memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
    	sizeof(config->PcieRpClkReqDetect));