HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30750
Change subject: mb: Move timestamp_add_now to northbridge x4x ......................................................................
mb: Move timestamp_add_now to northbridge x4x
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/northbridge/intel/x4x/raminit.c 9 files changed, 4 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30750/1
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e5e1110..49bec34 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -109,12 +109,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index eb534ca..4f12187 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -94,12 +94,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 2c1b586..0078995 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -174,12 +174,8 @@ halt(); }
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index a695c53..a866090 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -108,12 +108,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 78be08b..e9ee4b5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -156,12 +156,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 830bc73..13b8dcb 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -103,12 +103,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 36aa149..649fceb 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -96,12 +96,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 6d0bc97..4ba4514 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -89,12 +89,8 @@ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index b3b84d8..7c1603a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -34,6 +34,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> #include <mrc_cache.h> +#include <timestamp.h>
#define MRC_CACHE_VERSION 0
@@ -639,6 +640,7 @@ int fast_boot, cbmem_was_inited, cache_not_found; struct region_device rdev;
+ timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n");
pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); @@ -728,4 +730,6 @@ outb(0x6, 0xcf9); halt(); } + + timestamp_add_now(TS_AFTER_INITRAM); }