Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 26: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch...
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch...
PS25, Line 160: CONFIG_MAX_ROOT_PORTS
Ack
TGL only had 4 (TBT) of the CPU-side PCIe RPs; I think ADL has 7 (4 TBT, 2 PCIE gen4, 1 PCIE gen5)? can clean it up later
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Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
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