[coreboot-gerrit] Change in coreboot[master]: intel/common/block: Add gpmr common driver

[Arthur Heymans (Code Review)]

Attention is currently required from: Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63170 )

Change subject: intel/common/block: Add gpmr common driver
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Patch Set 14:

(3 comments)

File src/soc/intel/common/block/gpmr/gpmr.c:

https://review.coreboot.org/c/coreboot/+/63170/comment/ad15b6a8_8018bfb2 
PS14, Line 46: base & ~(GPMR_BASE_MASK << GPMR_BASE_SHIFT)
use IS_ALIGNED

https://review.coreboot.org/c/coreboot/+/63170/comment/f38e9a89_7d62fa91 
PS14, Line 47: printk(BIOS_ERR, "base is not 64-KiB aligned!\n");
Maybe make it more explicit (!IS_ALIGNED(base, 64 * KiB))?

File src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h:

https://review.coreboot.org/c/coreboot/+/63170/comment/f9393a18_2da50628 
PS14, Line 21: GPMR_BASE_SHIFT
I'm not sure how common this is, but I'm much more familiar with CPP definitions of shifts being left shifts and not right shifts? I'm wondering if the code would be better if you explicitly divide by 64K everywhere and use left shifts for both limit and base? My mind seems to conceptualize that register as such ^^