[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache

[Arthur Heymans (Code Review)]

Attention is currently required from: Andrey Petrov, Bora Guvendik, Jérémy Compostella, Paul Menzel, Ronak Kanabar, Shuo Liu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
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Patch Set 3:

(2 comments)

Patchset:

PS3: 
I'm a bit confused how this works. FSP-M needs to be relocated at runtime for this to work. I was not aware that this code exist in romstage or did I miss something?

Executing FSP-M in CAR is not a new thing. Intel APL/GLK does that, but in that case the FSP-M add is fixed at buildtime CONFIG_FSP_M_ADDR. Relocation is handled at buildtime. I'm wondering if that would not be a better idea than using the cbfs cache.?

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/81212/comment/dfb59052_00548f98 :
PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
Can you add an assert (I think makefile is easiest) that FSP-M is at least smaller than the cache?