Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47429 )
Change subject: nb/intel/sandybridge: Clarify RAM overclock options ......................................................................
nb/intel/sandybridge: Clarify RAM overclock options
Rewrite them to more accurately describe what they are about.
Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47429/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..b4834cd 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -44,19 +44,19 @@ System Agent/MRC.bin. You should answer Y.
config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES - bool "Ignore vendor programmed fuses that limit max. DRAM frequency" + bool "[OVERCLOCKING] Ignore CAPID fuses that limit max. DRAM frequency" default n depends on USE_NATIVE_RAMINIT help - Ignore the mainboard's vendor programmed fuses that might limit the - maximum DRAM frequency. By selecting this option the fuses will be - ignored and the only limits on DRAM frequency are set by RAM's SPD and - hard fuses in southbridge's clockgen. - Disabled by default as it might causes system instability. + Ignore the CAPID fuses and devicetree settings that might limit the + maximum DRAM frequency on overclocking-capable parts. By selecting + this option, the fuse values will be ignored and the only limits on + DRAM frequency are determined by SPD values and hard limits in the + northbridge's MPLL. Disabled by default as it can cause instability. Handle with care!
config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS - bool "Ignore XMP profile max DIMMs per channel" + bool "[OVERCLOCKING] Ignore XMP profile max DIMMs per channel" default n depends on USE_NATIVE_RAMINIT help