[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Mario Scheithauer (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 40:

(1 comment)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/bf5fac09_61ab5a41 
PS39, Line 432: params->PchPseTimedGpioPinEnable[6] = 1;
> Enabling PchPseTimedGpioPinEnable[6] will lead to an ASSERT when using FSP PV debug version. […]

I think I found the issue. To enable this TGpio6, it is also necessary to set the associated pin mux parameter - params->PchPseTgpio6PinMux = 0x8B81A203.
Do you need to add this and what about the other pin mux settings?