[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Skip GPIO configuration from FSP

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44913 )

Change subject: soc/intel/tigerlake: Skip GPIO configuration from FSP
......................................................................

soc/intel/tigerlake: Skip GPIO configuration from FSP

FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik 
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 2ba276d..4b68cb6 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -87,6 +87,9 @@
    dev = pcidev_path_on_root(PCH_DEVFN_ISH);
    m_cfg->PchIshEnable = is_dev_enabled(dev);

+	/* Skip GPIO configuration from FSP */
+	m_cfg->GpioOverride = 0x1;
+
    /* DP port config */
    m_cfg->DdiPortAConfig = config->DdiPortAConfig;
    m_cfg->DdiPortBConfig = config->DdiPortBConfig;