Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 2:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 87: int s3_save_nvram_early(u32 dword, int size, int nvram_pos) Separate commit, remove as unused and prototypes in hudson.h too. It's really yet another BIOSRAM implementation.
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 101: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) as above
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 133: pm_io_write8(0x2c, ioBase | 1); pm_io_write16() ?
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 134: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz this is just outb() put perhaps swapped parameter order.
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 229: int s3_save_nvram_early(u32 dword, int size, int nvram_pos) remove
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 242: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) remove
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 134: pm_io_write8(0x2c, ioBase | 1); pm_io_write16() perhaps?
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 135: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz outb()