Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode
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Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@9
PS1, Line 9: Intel's faulty LPC clock
Is that documented in some errata document?
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@12
PS1, Line 12:
Tested how?
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