Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30058
Change subject: cpu/via/nano: Implement POSTCAR stage ......................................................................
cpu/via/nano: Implement POSTCAR stage
Use postcar frame functions to set up an environment that the relocatable ramstage can use.
Untested
Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/via/car/cache_as_ram.inc M src/cpu/via/nano/Kconfig M src/cpu/via/nano/Makefile.inc M src/mainboard/via/epia-m850/romstage.c M src/northbridge/via/vx900/Makefile.inc M src/northbridge/via/vx900/memmap.c M src/northbridge/via/vx900/vx900.h 7 files changed, 36 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30058/1
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index b7803d8..cd27539 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -169,69 +169,9 @@ pushl %eax /* BIST */ call main
- /* - * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we - * get STACK up, we restore that. It is only needed if we - * want to go back. - */ - - /* We don't need CAR from now on. */ - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Set the default memory type and enable variable MTRRs. */ - /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN), %eax - wrmsr - - /* Enable caching for 0..CACHE_TMP_RAMTOP. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - movl $(0x0 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRR_PHYS_MASK(0), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Cache XIP_ROM area to speedup coreboot code. */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - invd - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl $CONFIG_RAMTOP, %esp - movl %esp, %ebp - call copy_and_run + /* Should never see this postcode */ + post_code(POST_DEAD_CODE)
.Lhlt: - post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index c7e7060..b789e45 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -29,6 +29,8 @@ select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + select POSTCAR_STAGE + select POSTCAR_CONSOLE
config DCACHE_RAM_BASE hex diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc index 43d0352..2a865ac 100644 --- a/src/cpu/via/nano/Makefile.inc +++ b/src/cpu/via/nano/Makefile.inc @@ -26,3 +26,5 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin
cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc + +postcar-y += ../car/exit_car.S \ No newline at end of file diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index dd303b7..7709709 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -98,4 +98,6 @@ /* FIXME: See if this is needed or take this out please */ /* Disable Memcard and SDIO */ pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4)); + + platform_enter_postcar(); } diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b..ec9edf3 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -48,4 +48,6 @@ bootblock-y += romstrap.ld bootblock-y += romstrap.S
+postcar-y += memmap.c + endif diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..82aedbf 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -19,6 +19,7 @@
#include "vx900.h"
+#include <cpu/x86/mtrr.h> #include <device/pci.h> #include <cbmem.h>
@@ -27,6 +28,8 @@ #define CHROME_9_HD_MIN_FB_SIZE 8 #define CHROME_9_HD_MAX_FB_SIZE 512
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + /* Helper to determine the framebuffer size */ void vx900_set_chrome9hd_fb_size(u32 size_mb) { @@ -126,3 +129,25 @@
return (void *)((tolm - fb_size) << 20); } + +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index a2a360a..9153fe2 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -37,6 +37,7 @@ u32 vx900_get_chrome9hd_fb_size(void); u8 vx900_int15_get_5f18_bl(void); uint64_t get_uma_memory_base(void); +void platform_enter_postcar(void);
/* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */