Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32035
Change subject: nb/intel/sandybridge: Move southbridge code to bd82x6x ......................................................................
nb/intel/sandybridge: Move southbridge code to bd82x6x
Move the southbridge code to bd82x6x folder similar to the lynxpoint implementation.
Untested.
Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 40 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32035/1
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index ad579c6..b923065 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -27,20 +27,6 @@
static void sandybridge_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index b49165c..6112c76 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,9 +28,8 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h>
-static void early_pch_init(void) +static void early_pch_reset_pmcon(void) { u8 reg8;
@@ -55,13 +54,8 @@ if (bist == 0) enable_lapic();
- pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); + /* Init LPC, GPIO, BARs, disable watchdog ... */ + early_pch_init();
/* Initialize superio */ mainboard_config_superio(); @@ -100,7 +94,7 @@
post_code(0x3b); /* Perform some initialization that must run before stage2 */ - early_pch_init(); + early_pch_reset_pmcon(); post_code(0x3c);
southbridge_configure_default_intmap(); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 23942fe..7fbc732 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,6 +19,8 @@ #include <ip_checksum.h> #include <device/pci_def.h> #include <delay.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h>
#include "pch.h" /* For DMI bar. */ @@ -368,3 +370,36 @@
init_dmi(); } + +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); +} + +void early_pch_init(void) +{ + pch_enable_lpc(); + + pch_enable_bars(); + + pch_generic_setup(); + + setup_pch_gpios(&mainboard_gpio_map); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 67b0d11..0097e15 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,7 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); +void early_pch_init(void);
struct southbridge_usb_port {