Attention is currently required from: Nico Huber, Subrata Banik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 )
Change subject: soc/inte/common: Add support to control coreboot and Intel SoC features ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/debug/debug_feature.c:
https://review.coreboot.org/c/coreboot/+/61380/comment/284a9afd_68c38f79 PS2, Line 28: cse_fw_update_disable
Assumption is, coreboot enables a feature by default and debug logic look for OEM SECTION if the f […]
Also, if I understood it correctly the default value for OEM region is 0xFF so that way, unless someone override it for debug purpose, it would always read as `1` and consider `update is enable` and upon resetting the desire bit for debug purpose (to skip CSE update), the code logic would read it `0`. Not sure if it make sense to refer default `1` as CSE FW update disable.
Please note, by default, coreboot gets 0xff if it reads from OEM SECTION. But, the expected value is "1" to enable debug feature.