Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3471
-gerrit
commit 8eec290f7beb6b0150855e8316ab5cd856ba2d4b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Jun 15 12:29:23 2013 +0300
bd82x6x: Fix early EHCI BAR programming
Change EHCI #2 to different BAR from EHCI #1.
Even if the ECHI controllers are not to be addressed, it is bad idea to set two different devices to claim the same PCI memory cycles.
Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/southbridge/intel/bd82x6x/early_usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index f4e526d..baf8c4f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -49,9 +49,9 @@ void enable_usb_bar(void) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd);
- /* USB Controller 1 */ + /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd);