[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE from _CRS

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80795?usp=email )

Change subject: soc/intel/xeon_sp: Drop SPI_BASE from _CRS
......................................................................

soc/intel/xeon_sp: Drop SPI_BASE from _CRS

The SPIBAR is a regulator BAR on the SPI PCI device. In case it's
hidden the fast_spi driver will generate the _CRS marking the BAR
as reserved.

Drop it from the uncore _CRS generation.

Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
3 files changed, 0 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80795/1

diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
index 8b24ba2..93b4c60 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
@@ -89,9 +89,6 @@
    	if (stack == 0) {
    		acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
    			VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-			acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-				(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-				SPI_BASE_SIZE);
    	}

/* Mem32 resource */
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 2e2b14a..247d1dd 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -111,9 +111,6 @@
    		if (socket == 0 && stack == 0) {
    			acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
    				VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-				acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-					(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-					SPI_BASE_SIZE);
    		}

/* Mem32 resource */
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index ca1cdf9..42927c0 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -107,9 +107,6 @@
    	if (socket == 0 && stack == 0) {
    		acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
    				       VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
-			acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
-					       (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
-					       SPI_BASE_SIZE);
    	}

/* Mem32 resource */