Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31262 )
Change subject: soc/intel/cannonlake: Add field to identify single channel memory ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/#/c/31262/11/src/soc/intel/cannonlake/cnl_memcfg... File src/soc/intel/cannonlake/cnl_memcfg_init.c:
https://review.coreboot.org/#/c/31262/11/src/soc/intel/cannonlake/cnl_memcfg... PS11, Line 61: mem_cfg->MemorySpdPtr00 = 0; Same comment as before. This is the default value. Probably okay to skip?
https://review.coreboot.org/#/c/31262/11/src/soc/intel/cannonlake/include/so... File src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h:
https://review.coreboot.org/#/c/31262/11/src/soc/intel/cannonlake/include/so... PS11, Line 115: zero to default 0 zero to default 0?
https://review.coreboot.org/#/c/31262/11/src/soc/intel/cannonlake/include/so... PS11, Line 116: existing boards like wilco/sarien. I don't think we need to explicitly mention mainboards here. Also, wilco/sarien doesn't use SPD from CBFS