[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47302 )

Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
......................................................................

soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's

Add a soc specific callback for getting the IIO IOAPIC enumeration ID.

Tested on ocp/deltalake.

Change-Id: Id504c2159066e6cddd01d30649921447bef17b12
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/nb_acpi.c
M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
6 files changed, 47 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/1

diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index c70945a..46f9c5f 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -90,23 +90,19 @@
    /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
 #if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
    const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
-	const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
 #endif

#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
    const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
-	const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 };
 #endif
    /* Local APICs */
    current = xeonsp_acpi_create_madt_lapics(current);

cur_index = 0;
    {
-		assert(cur_index < ARRAY_SIZE(ioapic_ids));
    	assert(cur_index < ARRAY_SIZE(gsi_bases));
-		int ioapic_id = ioapic_ids[cur_index];
    	int gsi_base = gsi_bases[cur_index];
-		current += add_madt_ioapic(current, 0, 0, ioapic_id,
+		current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID,
    				   hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase,
    				   gsi_base);
    	++cur_index;
@@ -117,9 +113,8 @@
    		const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
    		if (ri->Personality != TYPE_UBOX_IIO)
    			continue;
-			assert(cur_index < ARRAY_SIZE(ioapic_ids));
    		assert(cur_index < ARRAY_SIZE(gsi_bases));
-			int ioapic_id = ioapic_ids[cur_index];
+			int ioapic_id = soc_get_iio_ioapicid(socket, stack);
    		int gsi_base = gsi_bases[cur_index];
    		uint32_t ioapic_base = ri->IoApicBase;
    		/*
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
index 07c454e..2ebc9f1 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
@@ -12,7 +12,7 @@
 };

void get_iiostack_info(struct iiostack_resource *info);
-
+uint8_t soc_get_iio_ioapicid(int socket, int stack);
 void xeonsp_init_cpu_config(void);
 const IIO_UDS *get_iio_uds(void);
 void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 9e7072e..c8f52f2 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -336,3 +336,24 @@
    else
    	return -1;
 }
+
+uint8_t soc_get_iio_ioapicid(int socket, int stack)
+{
+	uint8_t ioapic_id = socket ? 0xf : 0x9;
+	switch (stack) {
+	case CSTACK:
+		break;
+	case PSTACK0:
+		ioapic_id += 1;
+		break;
+	case PSTACK1:
+		ioapic_id += 2;
+		break;
+	case PSTACK2:
+		ioapic_id += 3;
+		break;
+	default:
+		return 0xff;
+	}
+	return ioapic_id;
+}
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index 6cb6828..f14064d 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -190,15 +190,6 @@
 static unsigned long acpi_create_drhd(unsigned long current, int socket,
    int stack, const IIO_UDS *hob)
 {
-	int IoApicID[] = {
-		// socket 0
-		PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID,
-		PC04_IOAPIC_ID, PC05_IOAPIC_ID,
-		// socket 1
-		PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID,
-		PC10_IOAPIC_ID, PC11_IOAPIC_ID,
-	};
-
    uint32_t enum_id;
    unsigned long tmp = current;

@@ -237,7 +228,7 @@
    }

// Add IOAPIC entry
-	enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack];
+	enum_id = soc_get_iio_ioapicid(socket, stack);
    printk(BIOS_DEBUG, "    [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
    	"PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM);
    current += acpi_create_dmar_ds_ioapic(current, enum_id, bus,
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
index 93481c9..ef48485 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
@@ -12,7 +12,7 @@
 };

void get_iiostack_info(struct iiostack_resource *info);
-
+uint8_t soc_get_iio_ioapicid(int socket, int stack);
 void xeonsp_init_cpu_config(void);
 const IIO_UDS *get_iio_uds(void);
 void config_reset_cpl3_csrs(void);
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index f9eddb2..97950d4 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -421,4 +421,25 @@
    else
    	return -1;
 }
+
+uint8_t soc_get_iio_ioapicid(int socket, int stack)
+{
+	uint8_t ioapic_id = socket ? 0xf : 0x9;
+	switch (stack) {
+	case CSTACK:
+		break;
+	case PSTACK0:
+		ioapic_id += 1;
+		break;
+	case PSTACK1:
+		ioapic_id += 2;
+		break;
+	case PSTACK2:
+		ioapic_id += 3;
+		break;
+	default:
+		return 0xff;
+	}
+	return ioapic_id;
+}
 #endif