[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add pinmux support

[Shaunak Saha (Code Review)]

Hello Patrick Rudolph, Nick Vaccaro, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38452

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Add pinmux support
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soc/intel/tigerlake: Add pinmux support

TGL UPD value for selecting alternative native function pins.
TGL FSP does native pin mux by IP enable UPD and UART0, I2C4,
DMIC0, DMIC1, CNVi pins have alternative pin selection for
native fucntions. These UPD values are used by FSP for setting
alternative pin selecting and mux for these pins.

BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board

Change-Id: I51deba87fcd1cde248e0f73757acf97682879090
Signed-off-by: Shaunak Saha 
---
M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38452/4