Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5932
-gerrit
commit 853115e56c0d3372cb7c533b4649dc43a3d1d912 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Thu Jun 5 08:50:17 2014 +0200
mainboard/lenovo/x60/i915.c: Use define for `BSM`
Although it builds without any further chanegs, include the header
src/northbridge/intel/i945/i945.h
where `BSM` is defined.
Change-Id: I7c0a795338c34038169e082446907987364a0e88 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/mainboard/lenovo/x60/i915.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..2dc018c 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -31,6 +31,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <northbridge/intel/i945/i945.h> #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> #include <device/pci.h> @@ -138,7 +139,7 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED;
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);