Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86097?usp=email )
Change subject: mb/dell/haswell_latitude: Add E5440 ......................................................................
mb/dell/haswell_latitude: Add E5440
Change-Id: I415f8f03a8a7b1cbf8f1eddfd7b508a4eabbf8d7 Signed-off-by: Nicholas Chin nic.c3.14@gmail.com --- M src/mainboard/dell/haswell_latitude/Kconfig M src/mainboard/dell/haswell_latitude/Kconfig.name A src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt A src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c A src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c A src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb A src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c 7 files changed, 188 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/86097/1
diff --git a/src/mainboard/dell/haswell_latitude/Kconfig b/src/mainboard/dell/haswell_latitude/Kconfig index c01735d..36a4481 100644 --- a/src/mainboard/dell/haswell_latitude/Kconfig +++ b/src/mainboard/dell/haswell_latitude/Kconfig @@ -11,6 +11,13 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP
+config BOARD_DELL_LATITUDE_E5440 + select BOARD_DELL_HASWELL_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP + select MAINBOARD_USES_IFD_GBE_REGION + config BOARD_DELL_LATITUDE_E7240 select BOARD_DELL_HASWELL_LATITUDE_COMMON select BOARD_ROMSIZE_KB_8192 @@ -23,12 +30,14 @@ default "dell/haswell_latitude"
config MAINBOARD_PART_NUMBER + default "Latitude E5440" if BOARD_DELL_LATITUDE_E5440 default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240
config DEVICETREE default "devicetree_lp.cb" if INTEL_LYNXPOINT_LP
config VARIANT_DIR + default "e5440" if BOARD_DELL_LATITUDE_E5440 default "e7240" if BOARD_DELL_LATITUDE_E7240
config OVERRIDE_DEVICETREE diff --git a/src/mainboard/dell/haswell_latitude/Kconfig.name b/src/mainboard/dell/haswell_latitude/Kconfig.name index 499f783..dbcd427 100644 --- a/src/mainboard/dell/haswell_latitude/Kconfig.name +++ b/src/mainboard/dell/haswell_latitude/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_LATITUDE_E5440 + bool "Latitude E5440" + config BOARD_DELL_LATITUDE_E7240 bool "Latitude E7240" diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt b/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt new file mode 100644 index 0000000..ebfd3b7 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/data.vbt Binary files differ diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c b/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c new file mode 100644 index 0000000..aee5935 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/gpio.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_OUT_LOW, + [5] = LP_GPIO_OUT_LOW, + [6] = LP_GPIO_OUT_LOW, + [7] = LP_GPIO_OUT_LOW, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_HIGH, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = LP_GPIO_OUT_LOW, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = LP_GPIO_OUT_LOW, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_LOW, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_LOW, + [85] = LP_GPIO_OUT_LOW, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c b/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c new file mode 100644 index 0000000..4ae33ac --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805de, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805de), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb b/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb new file mode 100644 index 0000000..d0c2791 --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/overridetree.cb @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_d_hotplug" = "0" + + device domain 0 on + subsystemid 0x1028 0x05de inherit + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + end + end +end diff --git a/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c b/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c new file mode 100644 index 0000000..a7c462b --- /dev/null +++ b/src/mainboard/dell/haswell_latitude/variants/e5440/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_DOCK }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, +};