Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Deepti Deshatty.
Maulik V Vaghela has uploaded a new patch set (#7) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................
mb/adlrvp: Fix DDR5 Boot issue
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/7
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Gerrit-Change-Number: 50996
Gerrit-PatchSet: 7
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