[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40385 )

Change subject: soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
......................................................................

Patch Set 22:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx/... 
File src/soc/intel/xeon_sp/cpx/romstage.c:

https://review.coreboot.org/c/coreboot/+/40385/21/src/soc/intel/xeon_sp/cpx/... 
PS21, Line 24: 	arch_upd->StackBase = (void *) 0xfe930000;
> Can we do this as part of the device tree and not hardcode the configuration?

We have an IPS ticket with Intel. Intel agreed that this is a violation of FSP spec, and thus it will be fixed in near future (once we clear the critical issues). At that time, this part of code (hardcoding StackBase and StackSize) will be reverted, to use FSP_USES_CB_STACK instead.