Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8007
-gerrit
commit fbc9ea1c2a08134f93c61a89a34fbd814c9f50e1 Author: Duncan Laurie dlaurie@chromium.org Date: Thu May 22 08:25:36 2014 -0700
samus: Update for board revision 1.9
- Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234 TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 --- .../google/samus/acpi/haswell_pci_irqs.asl | 91 ----------- src/mainboard/google/samus/acpi/mainboard.asl | 169 ++++++++++++++++----- src/mainboard/google/samus/devicetree.cb | 15 +- src/mainboard/google/samus/gpio.h | 30 ++-- src/mainboard/google/samus/mainboard.c | 66 +------- src/mainboard/google/samus/onboard.h | 70 --------- src/mainboard/google/samus/pei_data.c | 22 +-- src/mainboard/google/samus/romstage.c | 18 ++- src/mainboard/google/samus/spd/Makefile.inc | 26 ++-- src/mainboard/google/samus/spd/hynix_4Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/spd.c | 11 +- src/mainboard/google/samus/spd/spd.h | 1 + 13 files changed, 246 insertions(+), 309 deletions(-)
diff --git a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl b/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 336a1ac..0000000 --- a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Haswell ULT */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, _SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 72bff6c..5a052b9 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,21 +14,17 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <mainboard/google/samus/onboard.h> - Scope (_SB) { Device (LID0) { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) + Name (_HID, EisaId("PNP0C0D")) + Method (_LID, 0) { - Store (_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) + Return (_SB.PCI0.LPCB.EC0.LIDS) }
// There is no GPIO for LID, the EC pulses WAKE# pin instead. @@ -44,49 +39,149 @@ Scope (_SB)
Device (TPAD) { - Name (_ADR, 0x0) + Name (_HID, EisaId("PNP0C0E")) Name (_UID, 1) + Name (_PRW, Package() { 13, 0x3 }) // GPIO13 + }
- // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source + Device (TSCR) + { Name (_HID, EisaId("PNP0C0E")) + Name (_UID, 2) + Name (_PRW, Package() { 14, 0x3 }) // GPIO14 + } +} + +Scope (_SB.PCI0.I2C0) +{ + Device (ATPB) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad Bootloader") + Name (_UID, 1) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.PCI0.I2C0", // ResourceSource + )
- VendorShort (ADDR) - { - BOARD_TRACKPAD_I2C_ADDR - } + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } })
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } }
- Device (TSCR) + Device (ATPA) { - Name (_ADR, 0x0) + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.PCI0.I2C0", // ResourceSource + ) + + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } +} + +Scope (_SB.PCI0.I2C1) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */
- VendorShort (ADDR) - { - BOARD_TOUCHSCREEN_I2C_ADDR + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } } } diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 3e87eca..8810c47 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -43,16 +43,17 @@ chip soc/intel/broadwell register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "0" + register "sio_acpi_mode" = "1"
- # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" + register "icc_clock_disable" = "0x013b0000"
# Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0"
device cpu_cluster 0 on device lapic 0 on end @@ -77,9 +78,9 @@ chip soc/intel/broadwell device pci 17.0 off end # SDIO device pci 19.0 off end # GbE device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index c98be4d..f68ecdf 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -34,7 +34,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ - PCH_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */ + PCH_GPIO_PIRQ, /* 9: NFC_INT (PIRQ) */ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ PCH_GPIO_UNUSED, /* 11: UNUSED */ PCH_GPIO_UNUSED, /* 12: UNUSED */ @@ -43,9 +43,9 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ PCH_GPIO_INPUT, /* 16: PCH_WP */ PCH_GPIO_UNUSED, /* 17: UNUSED */ - PCH_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_UNUSED, /* 20: UNUSED */ + PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */ PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ PCH_GPIO_UNUSED, /* 22: UNUSED */ PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */ @@ -69,12 +69,12 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ PCH_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */ - PCH_GPIO_PIRQ, /* 45: ACCEL_INT (PIRQW) */ - PCH_GPIO_PIRQ, /* 46: CODEC_INT_L (PIRQO) */ - PCH_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */ + PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */ + PCH_GPIO_OUT_HIGH, /* 47: SSD_RESET_L */ PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_INPUT, /* 49: HDMI_CEC */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ PCH_GPIO_UNUSED, /* 50: UNUSED */ PCH_GPIO_UNUSED, /* 51: UNUSED */ PCH_GPIO_INPUT, /* 52: SIM_DET */ @@ -88,10 +88,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 60: UNUSED */ PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SS5_L */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ - PCH_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */ - PCH_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_INPUT, /* 66: RAM_ID3 */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ @@ -116,10 +116,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 88: UNUSED */ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */ - PCH_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */ - PCH_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */ - PCH_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END };
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index fdc7d78..89303b9 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -33,73 +33,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "ec.h" -#include "onboard.h"
-static void mainboard_init(device_t dev) +void mainboard_suspend_resume(void) { - mainboard_ec_init(); }
-static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) +static void mainboard_init(device_t dev) { - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - BOARD_TRACKPAD_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - BOARD_TOUCHSCREEN_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_CODEC_NAME, /* name */ - BOARD_CODEC_IRQ, /* instance */ - BOARD_CODEC_I2C_BUS, /* segment */ - BOARD_CODEC_I2C_ADDR, /* bus */ - BOARD_CODEC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_NFC_NAME, /* name */ - BOARD_NFC_IRQ, /* instance */ - BOARD_NFC_I2C_BUS, /* segment */ - BOARD_NFC_I2C_ADDR, /* bus */ - BOARD_NFC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_NAME, /* name */ - BOARD_ACCEL_IRQ, /* instance */ - BOARD_ACCEL_I2C_BUS, /* segment */ - BOARD_ACCEL_I2C_ADDR, /* bus */ - BOARD_ACCEL_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_GYRO_NAME, /* name */ - BOARD_ACCEL_GYRO_IRQ, /* instance */ - BOARD_ACCEL_GYRO_I2C_BUS, /* segment */ - BOARD_ACCEL_GYRO_I2C_ADDR, /* bus */ - BOARD_ACCEL_GYRO_IRQ_TYPE, /* device */ - 0); /* function */ - - return len; + mainboard_ec_init(); }
// mainboard_enable is executed as first thing after @@ -108,7 +49,6 @@ static int mainboard_smbios_data(device_t dev, int *handle, static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); }
diff --git a/src/mainboard/google/samus/onboard.h b/src/mainboard/google/samus/onboard.h deleted file mode 100644 index d47d3c9..0000000 --- a/src/mainboard/google/samus/onboard.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#define BOARD_PIRQ_INTERRUPT 0 -#define BOARD_GPIO_INTERRUPT 1 -#define BOARD_GPIO_OFFSET 162 -#define GPIO_INTERRUPT(x) (BOARD_GPIO_OFFSET + (x)) - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ 27 /* PIRQL */ -#define BOARD_TRACKPAD_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TRACKPAD_WAKE_GPIO 13 /* GPIO13 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ -#define BOARD_TRACKPAD_I2C_ADDR 0x4b - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ 28 /* PIRQM */ -#define BOARD_TOUCHSCREEN_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b - -#define BOARD_CODEC_NAME "codec" -#define BOARD_CODEC_IRQ 30 /* PIRQO */ -#define BOARD_CODEC_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_CODEC_WAKE_GPIO 46 /* GPIO46 */ -#define BOARD_CODEC_I2C_BUS 1 /* I2C0 */ -#define BOARD_CODEC_I2C_ADDR 0x1a - -#define BOARD_NFC_NAME "nfc" -#define BOARD_NFC_IRQ GPIO_INTERRUPT(9) -#define BOARD_NFC_IRQ_TYPE BOARD_GPIO_INTERRUPT -#define BOARD_NFC_WAKE_GPIO 9 /* GPIO9 */ -#define BOARD_NFC_I2C_BUS 1 /* I2C0 */ -#define BOARD_NFC_I2C_ADDR 0x28 - -#define BOARD_ACCEL_NAME "accel" -#define BOARD_ACCEL_IRQ 29 /* PIRQN */ -#define BOARD_ACCEL_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_WAKE_GPIO 45 /* GPIO45 */ -#define BOARD_ACCEL_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_I2C_ADDR 0x0e - -#define BOARD_ACCEL_GYRO_NAME "accel_gyro" -#define BOARD_ACCEL_GYRO_IRQ 31 /* PIRQP */ -#define BOARD_ACCEL_GYRO_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_GYRO_WAKE_GPIO 47 /* GPIO47 */ -#define BOARD_ACCEL_GYRO_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_GYRO_I2C_ADDR 0x6b - -#endif diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c index c4e9c0b..04b86e0 100644 --- a/src/mainboard/google/samus/pei_data.c +++ b/src/mainboard/google/samus/pei_data.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P1: HOST PORT */ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL); - /* P2: EMPTY */ - pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP, + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); - /* P4: EMPTY */ - pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P5: WWAN */ pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); @@ -74,8 +74,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data_usb3_port(pei_data, 0, 1, 0, 0); /* P2: HOST PORT */ pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); - /* P4: SD CARD */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9af4ffb..9594287 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,12 +22,13 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> #include <mainboard/google/samus/spd/spd.h> -#include "gpio.h" +#include <mainboard/google/samus/gpio.h>
void mainboard_romstage_entry(struct romstage_params *rp) { @@ -35,6 +36,9 @@ void mainboard_romstage_entry(struct romstage_params *rp)
post_code(0x32);
+ printk(BIOS_INFO, "MLB: board version %d\n", + google_chromeec_get_board_version()); + /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init();
@@ -47,6 +51,16 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data;
+ /* + * http://crosbug.com/p/29117 + * Limit Broadwell SKU to 1333MHz and disable channel 1 + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.max_ddr3_freq = 1333; + pei_data.dimm_channel1_disabled = 3; + memset(pei_data.spd_data[1][0], 0, SPD_LEN); + } + romstage_common(rp);
/* diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index 657a09d..ccce912 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -21,15 +21,23 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
-# { GPIO69, GPIO68, GPIO67 } -SPD_SOURCES = empty # 0: { 0, 0, 0 } -SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } -SPD_SOURCES += empty # 2: { 0, 1, 0 } -SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } -SPD_SOURCES += empty # 4: { 1, 0, 0 } -SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } -SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } -SPD_SOURCES += empty # 7: { 1, 1, 1 } +# { GPIO66, GPIO69, GPIO68, GPIO67 } +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += empty # 0b0011 +SPD_SOURCES += empty # 0b0100 +SPD_SOURCES += empty # 0b0101 +SPD_SOURCES += samsung_4Gb # 0b0110 +SPD_SOURCES += empty # 0b0111 +SPD_SOURCES += hynix_4Gb # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += samsung_8Gb # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += hynix_8Gb # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex new file mode 100644 index 0000000..c63c303 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3-S8B 8Gb(x32, 2CS) +# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex new file mode 100644 index 0000000..14002c1 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS) +# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32 +92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 331fc6d..0409302 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -80,7 +80,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { - int spd_gpio[3]; + int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file; @@ -88,11 +88,14 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + spd_gpio[3] = get_gpio(SPD_GPIO_BIT3);
- spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | + (spd_gpio[1] << 1) | spd_gpio[0];
- printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", - spd_index, + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " + "GPIO%d=%d GPIO%d=%d)\n", spd_index, + SPD_GPIO_BIT3, spd_gpio[3], SPD_GPIO_BIT2, spd_gpio[2], SPD_GPIO_BIT1, spd_gpio[1], SPD_GPIO_BIT0, spd_gpio[0]); diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 98180fa..77540af 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -36,6 +36,7 @@ #define SPD_GPIO_BIT0 67 #define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT2 69 +#define SPD_GPIO_BIT3 66
struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);