Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43919 )
Change subject: mb/asrock/h110m: Relocate devicetree settings ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... PS2, Line 21: # Set @0x280-0x2ff I/O Range for SuperIO HWM : register "gen1_dec" = "0x007c0281"
Maybe move it to the LPC bridge (device pci 1f. […]
Done
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... PS2, Line 36: register "SkipExtGfxScan" = "0" : register "PrimaryDisplay" = "Display_PEG"
device pci 02. […]
I moved SkipExtGfxScan to PEG because it's what it is about. I didn't move PrimaryDisplay because it's about choosing between devices. There's `config ONBOARD_VGA_IS_PRIMARY` which should have been used instead of this option, I guess.
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... PS2, Line 42: register "DspEnable" = "0" : register "PchHdaVcType" = "Vc1"
also Intel HDA?
Done
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... PS2, Line 45: # Set LPC Serial IRQ mode : register "serirq_mode" = "SERIRQ_CONTINUOUS"
LPC bridge
Done
https://review.coreboot.org/c/coreboot/+/43919/2/src/mainboard/asrock/h110m/... PS2, Line 131: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" : register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" : register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" : register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" : register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" : register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" : register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" : register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" : register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" : register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" : register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" : register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" : register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
device pci 14. […]
Done