Attention is currently required from: Chris Wang. Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/52733
to review the following change.
Change subject: amd/cezanne: Add telemetry setting to UPD ......................................................................
amd/cezanne: Add telemetry setting to UPD
Add telemetry setting to UPD, the value comes from the SDLE testing.
BUG=b:182754399 TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3787638 Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 3 files changed, 23 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52733/1
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 6b6a28f..bb72494 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -68,6 +68,13 @@ uint8_t cppc_epp_max_range; uint8_t cppc_epp_min_range; uint8_t cppc_preferred_cores; + + /* telemetry settings */ + uint32_t telemetry_vddcrvddfull_scale_current; + uint32_t telemetry_vddcrvddoffset; + uint32_t telemetry_vddcrsocfull_scale_current; + uint32_t telemetry_vddcrsocoffset; + };
#endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 2528086..37b6115 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -118,5 +118,15 @@ /* S0i3 enable */ mcfg->s0i3_enable = config->s0ix_enable;
+ /* telemetry settings */ + mcfg->telemetry_vddcrvddfull_scale_current = + config->telemetry_vddcrvddfull_scale_current; + mcfg->telemetry_vddcrvddoffset = + config->telemetry_vddcrvddoffset; + mcfg->telemetry_vddcrsocfull_scale_current = + config->telemetry_vddcrsocfull_scale_current; + mcfg->telemetry_vddcrsocOffset = + config->telemetry_vddcrsocoffset; + fsp_fill_pcie_ddi_descriptors(mcfg); } diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 6e9a1f0..f01af85 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -102,8 +102,12 @@ /** Offset 0x04A4**/ uint8_t fch_ioapic_id; /** Offset 0x04A5**/ uint8_t sata_enable; /** Offset 0x04A6**/ uint8_t fch_reserved[32]; - /** Offset 0x04A7**/ uint8_t s0i3_enable; - /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57]; + /** Offset 0x04C6**/ uint8_t s0i3_enable; + /** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current; + /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; + /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; + /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; + /** Offset 0x04D7**/ uint8_t UnusedUpdSpace0[41]; /** Offset 0x0500**/ uint16_t UpdTerminator; } FSP_M_CONFIG;