Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33130 )
Change subject: mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree C ......................................................................
mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree C
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled.
BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Arcada.
Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 1799127..ebcf140 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -164,6 +164,9 @@
register "tcc_offset" = "1"
+ # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = {