Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20363
Change subject: soc/intel/skylake: storage: Add 2ms delay before exiting D3 ......................................................................
soc/intel/skylake: storage: Add 2ms delay before exiting D3
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0.
Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84.
To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0.
This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there.
BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days.
Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- M src/soc/intel/skylake/acpi/scs.asl 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/20363/1
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 1f89689..c2f50cc 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -85,6 +85,7 @@
/* Set bits 31, 6, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x80000045) + Sleep (2)
/* Set Power State to D0 */ Store (Zero, Local0) @@ -139,6 +140,7 @@
/* Set bits 31, 6, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x00000185) + Sleep (2)
/* Set Power State to D0 */ Store (Zero, Local0)