Alexander Couzens (lynxis@fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7030
-gerrit
commit a55626c7247d5f3220d126642abd256edc7f46ad Author: Alexander Couzens lynxis@fe80.eu Date: Wed Oct 8 03:53:53 2014 +0200
util/inteltool: add ibex peak default gpio registers
Default gpio registers taken from Intel documentation 5 Series Chipset
Change-Id: I41688e29fcd6e53c863ba908b2b5b27287fb1dc0 Signed-off-by: Alexander Couzens lynxis@fe80.eu --- util/inteltool/gpio.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dfb0819..7454fb2 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -258,6 +258,44 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +/* Default values for Ibex Peak mobile chipsets */ +static const gpio_default_t ib_pch_mobile_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; +/* Default values for Ibex Peak desktop chipsets */ +static const gpio_default_t ib_pch_desktop_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -417,6 +455,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(ib_pch_desktop_defaults); break; case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: case PCI_DEVICE_ID_INTEL_3400_MOBILE: @@ -428,6 +468,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(ib_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: