HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39821 )
Change subject: nb/i945: Split ramint into desktop and mobile version ......................................................................
nb/i945: Split ramint into desktop and mobile version
Change-Id: I763efcff97ee3d0f1c3df62102f22ee3b3f6a0fc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/i945/Makefile.inc C src/northbridge/intel/i945/raminit_i945gc.c R src/northbridge/intel/i945/raminit_i945gm.c 3 files changed, 68 insertions(+), 362 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39821/1
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index bae0589..34c9dce 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -23,7 +23,12 @@
romstage-y += romstage.c romstage-y += memmap.c -romstage-y += raminit.c +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC),y) +romstage-y += raminit_i945gc.c +else +romstage-y += raminit_i945gm.c +endif + romstage-y += early_init.c romstage-y += errata.c romstage-y += debug.c diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit_i945gc.c similarity index 90% copy from src/northbridge/intel/i945/raminit.c copy to src/northbridge/intel/i945/raminit_i945gc.c index 134d11f..d2adeba 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit_i945gc.c @@ -102,42 +102,28 @@
static int memclk(void) { - int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - - switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { + switch ((MCHBAR32(CLKCFG) >> 4) & 7) { case 1: return 400; case 2: return 533; case 3: return 667; default: printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + ((MCHBAR32(CLKCFG) >> 4) & 7)); } return -1; }
static u16 fsbclk(void) { - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; - case 1: return 533; - case 2: return 800; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 1066; + case 1: return 533; + case 2: return 800; + default: + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, + MCHBAR32(CLKCFG) & 7); } + return 0xffff; }
static int sdram_capabilities_max_supported_memory_frequency(void) @@ -827,62 +813,6 @@ return nc; }
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -/* Strength multiplier tables */ -static const u8 dual_channel_strength_multiplier[] = { - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 -}; - -static const u8 single_channel_strength_multiplier[] = { - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 -}; -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -936,7 +866,6 @@ 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 }; -#endif
static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { @@ -1013,24 +942,13 @@ MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x26262626; break; - case 533: - channeldll = 0x22222222; break; - case 667: - channeldll = 0x11111111; break; - } - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x33333333; break; - case 533: - channeldll = 0x24242424; break; - case 667: - channeldll = 0x25252525; break; - } + switch (sysinfo->memory_frequency) { + case 400: + channeldll = 0x33333333; break; + case 533: + channeldll = 0x24242424; break; + case 667: + channeldll = 0x25252525; break; }
for (i = 0; i < 4; i++) { @@ -1038,10 +956,8 @@ MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - } + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } }
@@ -1754,7 +1670,6 @@ { u32 clkcfg; u8 reg8; - u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
printk(BIOS_DEBUG, "Setting Memory Frequency... ");
@@ -1777,11 +1692,11 @@
switch (sysinfo->memory_frequency) { case 400: - clkcfg |= ((1 + offset) << 4); break; + clkcfg |= (1 << 4); break; case 533: - clkcfg |= ((2 + offset) << 4); break; + clkcfg |= (2 << 4); break; case 667: - clkcfg |= ((3 + offset) << 4); break; + clkcfg |= (3 << 4); break; default: die("Target Memory Frequency Error"); } @@ -1839,53 +1754,6 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) - static const u32 data_clock_crossing[] = { - 0x00100401, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x08040120, 0x00000000, /* DDR400 FSB533 */ - 0x00100401, 0x00000000, /* DDR533 FSB533 */ - 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0x04020120, 0x00000010, /* DDR400 FSB667 */ - 0x10040280, 0x00000040, /* DDR533 FSB667 */ - 0x00100401, 0x00000000, /* DDR667 FSB667 */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - }; - - static const u32 command_clock_crossing[] = { - 0x04020208, 0x00000000, /* DDR400 FSB400 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00060108, 0x00000000, /* DDR400 FSB533 */ - 0x04020108, 0x00000000, /* DDR533 FSB533 */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00040318, 0x00000000, /* DDR400 FSB667 */ - 0x04020118, 0x00000000, /* DDR533 FSB667 */ - 0x02010804, 0x00000000, /* DDR667 FSB667 */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - }; - -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) - /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1929,7 +1797,6 @@ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ }; -#endif
printk(BIOS_DEBUG, "Programming Clock Crossing...");
@@ -2156,21 +2023,6 @@ reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32;
- if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - - MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - - /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } - } - reg16 = MCHBAR16(UPMC2); reg16 &= 0xfc00; reg16 |= 0x0100; @@ -2474,22 +2326,17 @@ { u8 clocks[2] = { 0, 0 };
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -#define CLOCKS_WIDTH 2 -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -#define CLOCKS_WIDTH 3 -#endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << CLOCKS_WIDTH)-1; + clocks[0] |= (1 << 3) - 1;
if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[0] |= ((1 << 3) - 1) << 3;
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << CLOCKS_WIDTH)-1; + clocks[1] |= (1 << 3) - 1;
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[1] |= ((1 << 3) - 1) << 3;
#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals @@ -2726,10 +2573,7 @@ * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) - sdram_program_graphics_frequency(&sysinfo); - else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534);
/* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit_i945gm.c similarity index 90% rename from src/northbridge/intel/i945/raminit.c rename to src/northbridge/intel/i945/raminit_i945gm.c index 134d11f..74c5bbc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit_i945gm.c @@ -102,42 +102,28 @@
static int memclk(void) { - int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - - switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { + switch (((MCHBAR32(CLKCFG) >> 4) & 7) - 1) { case 1: return 400; case 2: return 533; case 3: return 667; default: printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + ((MCHBAR32(CLKCFG) >> 4) & 7) - 1); } return -1; }
static u16 fsbclk(void) { - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; - case 1: return 533; - case 2: return 800; - default: - printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, - MCHBAR32(CLKCFG) & 7); - } - return 0xffff; + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 400; + case 1: return 533; + case 3: return 667; + default: + printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, + MCHBAR32(CLKCFG) & 7); } + return 0xffff; }
static int sdram_capabilities_max_supported_memory_frequency(void) @@ -827,7 +813,6 @@ return nc; }
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -882,61 +867,6 @@ 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -static const u8 dual_channel_strength_multiplier[] = { - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33 -}; - -static const u8 single_channel_strength_multiplier[] = { - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, - 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 -}; -#endif
static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { @@ -1013,24 +943,13 @@ MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
/* We drive both channels with the same speed */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x26262626; break; - case 533: - channeldll = 0x22222222; break; - case 667: - channeldll = 0x11111111; break; - } - } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - switch (sysinfo->memory_frequency) { - case 400: - channeldll = 0x33333333; break; - case 533: - channeldll = 0x24242424; break; - case 667: - channeldll = 0x25252525; break; - } + switch (sysinfo->memory_frequency) { + case 400: + channeldll = 0x26262626; break; + case 533: + channeldll = 0x22222222; break; + case 667: + channeldll = 0x11111111; break; }
for (i = 0; i < 4; i++) { @@ -1038,10 +957,6 @@ MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; - } } }
@@ -1754,8 +1669,7 @@ { u32 clkcfg; u8 reg8; - u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; - + printk(BIOS_DEBUG, "Setting Memory Frequency... ");
clkcfg = MCHBAR32(CLKCFG); @@ -1777,11 +1691,11 @@
switch (sysinfo->memory_frequency) { case 400: - clkcfg |= ((1 + offset) << 4); break; + clkcfg |= (2 << 4); break; case 533: - clkcfg |= ((2 + offset) << 4); break; + clkcfg |= (3 << 4); break; case 667: - clkcfg |= ((3 + offset) << 4); break; + clkcfg |= (4 << 4); break; default: die("Target Memory Frequency Error"); } @@ -1839,7 +1753,6 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1884,52 +1797,6 @@ 0xffffffff, 0xffffffff, /* nonexistent */ };
-#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) - /* i945 G/P */ - static const u32 data_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x10080201, 0x00000000, /* DDR400 FSB533 */ - 0x00100401, 0x00000000, /* DDR533 FSB533 */ - 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x04020108, 0x00000000, /* DDR400 FSB800 */ - 0x00020108, 0x00000000, /* DDR533 FSB800 */ - 0x00080201, 0x00000000, /* DDR667 FSB800 */ - - 0x00010402, 0x00000000, /* DDR400 FSB1066 */ - 0x04020108, 0x00000000, /* DDR533 FSB1066 */ - 0x08040110, 0x00000000, /* DDR667 FSB1066 */ - }; - - static const u32 command_clock_crossing[] = { - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x00010800, 0x00000402, /* DDR400 FSB533 */ - 0x01000400, 0x00000200, /* DDR533 FSB533 */ - 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */ - - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - 0xffffffff, 0xffffffff, /* nonexistent */ - - 0x02010804, 0x00000000, /* DDR400 FSB800 */ - 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020130, 0x00000008, /* DDR667 FSB800 */ - - 0x00020904, 0x00000000, /* DDR400 FSB1066 */ - 0x02010804, 0x00000000, /* DDR533 FSB1066 */ - 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ - }; -#endif
printk(BIOS_DEBUG, "Programming Clock Crossing...");
@@ -2156,19 +2023,17 @@ reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32;
- if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (i945_silicon_revision() > 1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; }
reg16 = MCHBAR16(UPMC2); @@ -2474,22 +2339,17 @@ { u8 clocks[2] = { 0, 0 };
-#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) -#define CLOCKS_WIDTH 2 -#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) -#define CLOCKS_WIDTH 3 -#endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << CLOCKS_WIDTH)-1; + clocks[0] |= (1 << 2) - 1;
if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[0] |= ((1 << 2) - 1) << 2;
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << CLOCKS_WIDTH)-1; + clocks[1] |= (1 << 2) - 1;
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; + clocks[1] |= ((1 << 2)-1) << 2;
#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals @@ -2726,10 +2586,7 @@ * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) - sdram_program_graphics_frequency(&sysinfo); - else - pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + sdram_program_graphics_frequency(&sysinfo);
/* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo);