Attention is currently required from: char, Felix Held.
Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 )
Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ......................................................................
Patch Set 1:
(9 comments)
Commit Message:
PS1: Missing Signed-off-by line
Patchset:
PS1: I would split the ITE8987e stuff to a separate commit
File src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/72788/comment/832ca50e_4c866318 PS1, Line 39: # Enable S0ix : register "s0ix_enable" = "1" : register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h : register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h : register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h : register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h Please change to tabs to be consistent with the rest of the file (seems like tabs are preferred anyway)
https://review.coreboot.org/c/coreboot/+/72788/comment/657d4d63_7850e3e5 PS1, Line 129: register "PcieRpMaxPayload[0]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[4]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[8]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[10]" = "RpMaxPayload_128" Tabs
https://review.coreboot.org/c/coreboot/+/72788/comment/9812742e_ace6b9e8 PS1, Line 149: register "PcieRpClkReqSupport[0]" = "0" : register "PcieRpClkReqSupport[4]" = "0" : register "PcieRpClkReqSupport[8]" = "0" : register "PcieRpClkReqSupport[10]" = "0" : : register "PcieRpClkReqNumber[0]" = "0" # Nvidia GPU : register "PcieRpClkReqNumber[4]" = "0" # NVME drive : register "PcieRpClkReqNumber[8]" = "0" # Wifi : register "PcieRpClkReqNumber[10]" = "0" # LPC Tabs
https://review.coreboot.org/c/coreboot/+/72788/comment/cc8dfe48_ec8b0d73 PS1, Line 215: device lapic 0 on end As of commit 69cd729c0c (mb/*: Remove lapic from devicetree) this line should be removed
https://review.coreboot.org/c/coreboot/+/72788/comment/7ce8aadf_3b882399 PS1, Line 263: chip superio/ite/it8987e # 'on' for everything returned from superiotool /w vendor ROM Many lines in this chip instance have tab/space issues
https://review.coreboot.org/c/coreboot/+/72788/comment/5fbbfa4c_7372b17e PS1, Line 358: chip drivers/crb : device mmio 0xfed40000 on end # this is the Intel PTT iTPM : end Tabs
https://review.coreboot.org/c/coreboot/+/72788/comment/9eb3393f_20ac9c6c PS1, Line 360: end nit: Fix alignment with corresponding chip line in line 358