Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41011 )
Change subject: soc/intel/common: Add ASL for TCSS PCI segment ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41011/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41011/2//COMMIT_MSG@9 PS2, Line 9: PCI1 device been created based on TCSS_PCIE_SEGMENT selection : from MB Kconfig I would like to know more about the motivation and reasoning behind this change. Also, how was this tested?
https://review.coreboot.org/c/coreboot/+/41011/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl:
https://review.coreboot.org/c/coreboot/+/41011/2/src/soc/intel/common/block/... PS2, Line 34: /* PCI Memory Region (TLUD - 0xdfffffff) */ : DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, : NonCacheable, ReadWrite, : 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, : 0xE0000000,,, PM01) : : /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ : QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, : NonCacheable, ReadWrite, : 0x00000000, 0x10000, 0x1ffff, 0x00000000, : 0x10000,,, PM02) These are exported by both the northbridge.asl MCHC device and PCI1 device?