Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39167
to look at the new patch set (#3).
Change subject: soc/tigerlake: Correct FSP log interface ......................................................................
soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as feafult and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 --- M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39167/3