Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47204 )
Change subject: mb/google/dedede/var/drawcia_legacy: Enable microcode in-field update ......................................................................
mb/google/dedede/var/drawcia_legacy: Enable microcode in-field update
This enables the top swap based microcode in-field update.
Change-Id: I5697799e3224965d321c284872f494ade9f2f1eb Signed-off-by: Sugnan Prabhu S sugnan.prabhu.s@intel.com --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/chromeos-ucode-32MiB.fmd 3 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47204/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 44d6910..4a98bb6 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -74,6 +74,8 @@ string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-ucode.fmd" \ if INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE && BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-ucode-32MiB.fmd" \ + if INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE && BOARD_ROMSIZE_KB_32768 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 238b4ca..a84a4e4 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -33,6 +33,8 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A select DRIVERS_INTEL_MIPI_CAMERA + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK_IPU
config BOARD_GOOGLE_MADOO diff --git a/src/mainboard/google/dedede/chromeos-ucode-32MiB.fmd b/src/mainboard/google/dedede/chromeos-ucode-32MiB.fmd new file mode 100644 index 0000000..29ebb4a --- /dev/null +++ b/src/mainboard/google/dedede/chromeos-ucode-32MiB.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xf00000 + RW_SECTION_A@0xf00000 0x3d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3bffc0 + RW_FWID_A@0x3cffc0 0x40 + } + RW_SECTION_B@0x12d0000 0x3d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3bffc0 + RW_FWID_B@0x3cffc0 0x40 + } + RW_MISC@0x16a0000 0x60000 { + RW_UCODE_STAGED@0 0x20000 + UNIFIED_MRC_CACHE(PRESERVE)@0x20000 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x50000 0x4000 + RW_SHARED@0x54000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x58000 0x2000 + RW_NVRAM(PRESERVE)@0x5a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +}