Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32052
Change subject: Doc/mb/asrock/h110m: Fix the links ......................................................................
Doc/mb/asrock/h110m: Fix the links
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M Documentation/mainboard/asrock/h110m-dvs.md 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32052/1
diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 5a3bb3e..8ceb7c8 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -5,9 +5,9 @@ ## Required proprietary blobs
Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. -Intel company provides [Firmware Support Package (2.0)](../../Documentation/soc/intel/fsp/index.md) +Intel company provides [Firmware Support Package (2.0)](../../../Documentation/soc/intel/fsp/index.md) (intel FSP 2.0) to initialize this generation silicon. Please see this -[document](../../Documentation/soc/intel/code_development_model/code_development_model.md). +[document](../../../Documentation/soc/intel/code_development_model/code_development_model.md).
FSP Information:
@@ -62,7 +62,7 @@ the BIOS region of the flash is writable. If you wish to change any other region, such as the Management Engine or firmware descriptor, then an external programmer is required (unless you find a clever way around -the flash protection). More information about this [here](../../Documentation/flash_tutorial/index.md). +the flash protection). More information about this [here](../../../Documentation/flash_tutorial/index.md).
### External programming