Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31056 )
Change subject: soc/intel/cannonlake: Export function to set After G3 state ......................................................................
soc/intel/cannonlake: Export function to set After G3 state
Export the SOC level function to set the After G3 state so it can be changed by the mainboard. The setting will be restored by a normal boot but in some circumstances coreboot wants to ensure that it will be powered up again after a reset.
BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot and ensure the host does not power off after the cr50 initiated reset.
Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/31056 Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/pmc.c 2 files changed, 5 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 992e60d..c3957d3 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -162,4 +162,8 @@ #define SCIS_IRQ21 5 #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 + +struct device; +void pmc_set_afterg3(struct device *dev, int s5pwr); + #endif diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 4dabb2e..e111e94 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -30,7 +30,7 @@ * Set which power state system will be after reapplying * the power (from G3 State) */ -static void pmc_set_afterg3(struct device *dev, int s5pwr) +void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; uint8_t *pmcbase = pmc_mmio_regs();