Attention is currently required from: Furquan Shaikh, Mariusz Szafrański, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Angel Pons, Michal Motyl, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51767 )
Change subject: soc/intel: Refactor common GPIO code ......................................................................
Patch Set 7:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51767/comment/7feae1d5_9157c47e PS7, Line 7: Refactor common GPIO code
I think it would be good to have a summary that gives a hint about what is really being done? […]
Ack
https://review.coreboot.org/c/coreboot/+/51767/comment/483dc4db_b63bb25c PS7, Line 12: some new PM feature has added
additional bits are defined in the MISCCFG register for GPIO PM control. […]
Ack
File src/soc/intel/alderlake/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/51767/comment/919f915f_4f04abab PS7, Line 13: MISCCFG_ENABLE_GPIO_PM_CONFIG
I think we should rename this to MISCCFG_GPIO_PM_CONFIG_BITS. […]
Ack
File src/soc/intel/apollolake/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/51767/comment/eecb8f42_8e45001f PS7, Line 13:
Add a comment saying that APL/GLK do not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/denverton_ns/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/51767/comment/1437cf07_3c22e25e PS7, Line 35:
Add a comment saying that denverton does not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/skylake/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/51767/comment/58b7ea75_d50d89db PS7, Line 11:
Add a comment saying that SKL does not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/xeon_sp/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/51767/comment/03b038bd_b5948b43 PS7, Line 9: 0
Is this correct?
Yes Xeon doesn't have PM bits either