Attention is currently required from: Furquan Shaikh, Mariusz Szafrański, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Angel Pons, Michal Motyl, Andrey Petrov, Patrick Rudolph.
7 comments:
Commit Message:
Patch Set #7, Line 7: Refactor common GPIO code
I think it would be good to have a summary that gives a hint about what is really being done? […]
Ack
Patch Set #7, Line 12: some new PM feature has added
additional bits are defined in the MISCCFG register for GPIO PM control. […]
Ack
File src/soc/intel/alderlake/include/soc/gpio.h:
Patch Set #7, Line 13: MISCCFG_ENABLE_GPIO_PM_CONFIG
I think we should rename this to MISCCFG_GPIO_PM_CONFIG_BITS. […]
Ack
File src/soc/intel/apollolake/include/soc/gpio.h:
Add a comment saying that APL/GLK do not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/denverton_ns/include/soc/gpio.h:
Add a comment saying that denverton does not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/skylake/include/soc/gpio.h:
Add a comment saying that SKL does not support GPIO PM bits in MISCCFG register.
Ack
File src/soc/intel/xeon_sp/include/soc/gpio.h:
Is this correct?
Yes Xeon doesn't have PM bits either
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