Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29909
Change subject: soc/intel/fsp_baytrail: Implement postcar stage ......................................................................
soc/intel/fsp_baytrail: Implement postcar stage
Change-Id: I692bbffe9c37367430191266023ce4e2cf1342a9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc A src/soc/intel/fsp_baytrail/exit_car_fsp.S 3 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29909/1
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7d82f3f..4c5a141 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -46,6 +46,8 @@
# Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN + select POSTCAR_STAGE + select POSTCAR_CONSOLE
config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index d8c4f71..a465655 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -30,6 +30,7 @@
ramstage-y += memmap.c romstage-y += memmap.c +postcar-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c @@ -60,4 +61,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
+postcar-y += exit_car_fsp.S + endif diff --git a/src/soc/intel/fsp_baytrail/exit_car_fsp.S b/src/soc/intel/fsp_baytrail/exit_car_fsp.S new file mode 100644 index 0000000..4ac580c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/exit_car_fsp.S @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching which can be overwritten + * after the API call. More info can be found in the FSP Integration + * Guide included with the FSP binary. + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov post_car_stack_top, %esp + + /* Call C code */ + call main