[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS

[huayang duan (Code Review)]

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39034 )

Change subject: soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS
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soc/mediatek/mt8183: Set correct threshold of EMI bandwidth for DVFS

The threshold of EMI bandwidth should have difference setting
for discrete and EMCP DDR, because the discrete DDR and EMCP DDR
have different DVFS tables.

BRANCH=kukui
BUG=none
TEST=bootup pass

Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/emi.c
1 file changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/39034/1

diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index cf104f8..7e535dc 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -299,8 +299,10 @@

setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
    setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
-
-	write32(&emi_regs->bwct0, 0x0a000705);
+	if (CONFIG_MT8183_DRAM_EMCP)
+		write32(&emi_regs->bwct0, 0x0d000705);
+	else
+		write32(&emi_regs->bwct0, 0x0a000705);
    write32(&emi_regs->bwct0_3rd, 0x0);

/* EMI QoS 0.5 */