[coreboot-gerrit] Change in coreboot[master]: qualcomm/sc7280: Cleanup common clock driver for sc7280

[Ravi kumar (Code Review)]

Attention is currently required from: Taniya Das.
Hello Taniya Das,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/57448

to review the following change.

Change subject: qualcomm/sc7280: Cleanup common clock driver for sc7280
......................................................................

qualcomm/sc7280: Cleanup common clock driver for sc7280

Add support for Zonda PLL enable for CPU in common clock driver.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Taniya Das 
Change-Id: I795e6cf33ee98204c40ebfafa990be2c24667157
---
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7280/clock.c
3 files changed, 26 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/57448/1

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index e83f979..09cd95c 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -236,6 +236,29 @@
    return CB_SUCCESS;
 }

+enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg)
+{
+	setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT));
+
+	/*
+	* H/W requires a 1us delay between disabling the bypass and
+	* de-asserting the reset.
+	*/
+	udelay(1);
+	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
+	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
+
+	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+		printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n");
+		return CB_ERR;
+	}
+
+	setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK);
+	setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT));
+
+	return CB_SUCCESS;
+}
+
 /* Bring subsystem out of RESET */
 void clock_reset_subsystem(u32 *misc, u32 shft)
 {
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index b924194..0911827 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -155,6 +155,8 @@
    				bool enable, int br_enable);
 enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg);

+enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg);
+
 struct aoss {
    u8 _res0[0x50020];
    u32 aoss_cc_reset_status;
diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c
index 871fb9b..07a575b 100644
--- a/src/soc/qualcomm/sc7280/clock.c
+++ b/src/soc/qualcomm/sc7280/clock.c
@@ -255,7 +255,6 @@
    clock_enable(&gcc->qspi_core_cbcr);
 }

-
 void clock_enable_qup(int qup)
 {
    struct qupv3_clock *qup_clk;
@@ -412,7 +411,7 @@
    if (clk_type >= MDSS_CLK_COUNT)
    	return CB_ERR;

-	/* Enable clock*/
+	/* Enable clock */
    return clock_enable(mdss_cbcr[clk_type]);
 }