[coreboot-gerrit] Change in ...coreboot[master]: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32842 )

Change subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
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southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw

outw takes (value, addr) not (addr, value)

Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622
Signed-off-by: Hannah Williams 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Martin Roth 
---
M src/southbridge/intel/fsp_rangeley/early_init.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 32e3bb5..cec7a31 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -40,8 +40,8 @@
    /* Disable the watchdog reboot and turn off the watchdog timer */
    write8((void *)(DEFAULT_PBASE + PMC_CFG),
           read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT);	// disable reboot on timer trigger
-	outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
-		TCO_TMR_HALT);	// disable watchdog timer
+	outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT,
+		DEFAULT_ABASE + TCO1_CNT);	// disable watchdog timer

printk(BIOS_DEBUG, " done.\n");