Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42282 )
Change subject: soc/intel/tgl: Disable hybrid storage mode in recovery mode ......................................................................
soc/intel/tgl: Disable hybrid storage mode in recovery mode
This is WA to initialize NVME with CSE Lite in recovery mode. CSME Lite does not support hybrid storage dynamic configuration in RO. Hence, hybrid storage mode is disabled in recovery mode for CSME Lite until the functionality is supported by CSE Lite RO.
BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721
Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42282/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c old mode 100644 new mode 100755 index 926d8eb..e931a22 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> +#include <security/vboot/vboot_common.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -251,7 +252,17 @@ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
/* Enable Hybrid storage auto detection */ - params->HybridStorageMode = config->HybridStorageMode; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) { + /* + * Since CSME Lite SKU does not support hybrid storage dynamic + * configuration in recovery boot mode, dynamic configuration is + * disabled as a temporary WA until the fix is available. + */ + printk(BIOS_DEBUG, "cse_lite: recovery mode enabled\n"); + params->HybridStorageMode = 0; + } else { + params->HybridStorageMode = config->HybridStorageMode; + }
/* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {