[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/cannonlake: Add PsysPmax setting

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31505

Change subject: src/soc/intel/cannonlake: Add PsysPmax setting
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src/soc/intel/cannonlake: Add PsysPmax setting

This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.

BUG=None
BRANCH=None
TEST=Set psys_pmax to an exmaple value eg 101 in DT && put debug code
     in FSP to print the PsysPmax value before sending to Pcode, ensure
     the setting is correctly programmed.

Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31505/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index cb9ad38..1f26f1e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -216,6 +216,8 @@
    uint32_t tdp_psyspl3_dutycycle;
    /* PL4 Value in Watts */
    uint32_t tdp_pl4;
+	/* Estimated maximum platform power in Watts */
+	uint16_t psys_pmax;

/* Intel Speed Shift Technology */
    uint8_t speed_shift_enable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index c276c86..e7c1358 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -88,6 +88,13 @@

mainboard_silicon_init_params(params);

+	/* Set PsysPmax if it is available from DT */
+	if (config->psys_pmax) {
+		/* PsysPmax is in unit of 1/8 Watt */
+		tconfig->PsysPmax = config->psys_pmax * 8;
+		printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
+	}
+
    /* Unlock upper 8 bytes of RTC RAM */
    params->PchLockDownRtcMemoryLock = 0;