Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29427
Change subject: sb/intel: Deduplicate vbnv_cmos_failed ......................................................................
sb/intel: Deduplicate vbnv_cmos_failed
Move all implementations to into common folder. Allows all Intel based platforms to use VBOOT_VBNV_CMOS.
Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c 8 files changed, 28 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29427/1
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index f1ac4f0..6c1df29 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -23,7 +23,6 @@ #include <arch/acpi.h> #include <console/console.h> #include <rules.h> -#include <security/vboot/vbnv.h>
#if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) @@ -63,17 +62,3 @@ } #endif
-int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0..bb0d5c4 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -100,9 +100,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#endif - -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); #endif
/* PM I/O Space */ diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 249d249..c27d339 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -52,4 +52,5 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
+romstage-y += pmutil.c endif diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index ac72eba..0cab015 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -19,11 +19,14 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> +#include <security/vboot/vbnv.h>
#include "pmutil.h"
@@ -234,3 +237,18 @@
return reg16; } + +int rtc_failure(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif + return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); +} + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 26134d9..af7bf97 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,6 +104,11 @@ #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a
+#define GEN_PMCON_3 0xa4 +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + u16 get_pmbase(void);
u16 reset_pm1_status(void); @@ -127,4 +132,7 @@ void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
+/* Return non-zero when RTC failure happened. */ +int rtc_failure(void); + #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b09fed..7289929 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include <arch/acpigen.h> #include <cbmem.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/pmutil.h>
#define NMI_OFF 0
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 489b565..76b9299 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -172,9 +172,6 @@ void enable_gpe(u32 mask); void disable_gpe(u32 mask);
-/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h> diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index e96d683..0916d2d 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,7 +24,6 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> -#include <security/vboot/vbnv.h> #include "pch.h"
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) @@ -555,17 +554,3 @@ outl(gpe0_en, get_pmbase() + gpe0_reg); }
-int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -}