[coreboot-gerrit] Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation

[Maxim Polyakov (Code Review)]

Attention is currently required from: Michał Żygowski, Michał Kopeć, Angel Pons.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 )

Change subject: util/intelp2m: Add support for Alder Lake macro generation
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Patch Set 5: Code-Review+1

(2 comments)

File util/intelp2m/platforms/adl/macro.go:

https://review.coreboot.org/c/coreboot/+/63403/comment/ed72f526_4140a4bf 
PS4, Line 52: 	var remapping = map[uint8]uint32{
> I can see the following reset configs for GPP_I for example: […]

let's add RST_PWROK to the map?

var remapping = map[uint8]uint32{
    	0: common.RST_RSMRST << common.PadRstCfgShift,
    	1: common.RST_DEEP << common.PadRstCfgShift,
    	2: common.RST_PLTRST << common.PadRstCfgShift,
    	3: common.RST_PWROK << common.PadRstCfgShift,
    }

File util/intelp2m/platforms/adlh/macro.go:

https://review.coreboot.org/c/coreboot/+/63403/comment/7736ca17_97e170b6 
PS2, Line 20: 	MAX_DW_NUM  = common.MAX_DW_NUM
> ADL PCH-H EDS describes only DW0 and DW1.

Perhaps the PCH-LP contains DW2 and DW3 registers?

In any case, we will be able to parse the DW2/3 registers only after they are printed in the inteltool dump.

I have some ideas how to do this - https://review.coreboot.org/c/coreboot/+/55984, but unfortunately I don't have the necessary platform (and documentation) to test these changes.