[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31245 )

Change subject: soc/intel/{skylake,cannonlake,icelake}: Correct GPIO IRQ start map
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31245/2/src/soc/intel/cannonlake/include/soc... 
File src/soc/intel/cannonlake/include/soc/itss.h:

https://review.coreboot.org/#/c/31245/2/src/soc/intel/cannonlake/include/soc... 
PS2, Line 21: PCI devices are reserving IRQ till 34
This will be violating the interrupt controller requirements that IRQ > 29 should not have more than one interrupt source. GPIO controller already claims INTSEL 29-34. If PCI devices are also doing that, won't that lead to issues?