1 comment:
File src/soc/intel/cannonlake/include/soc/itss.h:
Patch Set #2, Line 21: PCI devices are reserving IRQ till 34
This will be violating the interrupt controller requirements that IRQ > 29 should not have more than one interrupt source. GPIO controller already claims INTSEL 29-34. If PCI devices are also doing that, won't that lead to issues?
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