[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Meera Ravindranath.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63299 )

Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings
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Patch Set 2:

(1 comment)

File src/include/cpu/intel/cpu_ids.h:

https://review.coreboot.org/c/coreboot/+/63299/comment/9acd17e2_10bd50d2 
PS2, Line 54: #define CPUID_ALDERLAKE_J0		0x906a0
            : #define CPUID_ALDERLAKE_Q0		0x906a1
            : #define CPUID_ALDERLAKE_K0		0x906a2
            : #define CPUID_ALDERLAKE_R0		0x906a4
> Out of curiosity, are these CPU IDs paired with a specific PCH type?

Yes sorrect. ADL-P is SoC hence PCH & CPU is packed in 1 single Die